The present invention relates to a read-only memory device, the content of which can be programmed electrically, that is, a programmable read-only memory device (hereinafter simply called as a "P-ROM"). More particularly, the present invention relates to a test circuit for checking whether or not programming data into a P-ROM can be conducted without failure.
Recently, P-ROMs have been gained an extremely wide range of applications in the field of data processing and control because of their advantage in that a user can freely program the data thereinto.
So-called "junction destruction type" and "fuse type" P-ROM's are well-known as bipolar P-ROM's. The junction destruction type P-ROM includes memory cells arrayed in a matrix form and each consisting of one bipolar transistor of a base-open type, which has a collector and an emitter connected to one row line and one column line, respectively. Programming data in a P-ROM of this type is performed by supplying a considerably large programming current to the selected memory cell to destroy, i.e., short-circuit the base-emitter junction of the cell transistor. As a result, the transistor of the programmed memory cell operates merely as a diode to allow a reading-out current to flow from the column line to the row line in data read-out operation. On the other hand, the base-emitter junction of the transistor in the non-programmed memory cells prevents the current from flowing from the column to row lines.
In the fuse type P-ROM, each memory cell consists of a fuse and a diode connected in series between each column line and each row line. Data programming in this type is carried out by supplying a programming current to the selected memory cell to melt the fuse. In the read-out operation, the reading-out current does not flow from the selected column line to the selected row line, when the programmed memory cell is disposed at the intersection of the selected column and row lines. If the selected memory cell is not programmed, the reading-out current flows between the column and row lines. The fuse type P-ROM is, however, disadvantageous in that the melted fuse is scattered over the surface of the P-ROM chip to adversely affect the electrical performances of the P-ROM. The junction destruction type P-ROM is preferable in this respect.
It will be apparent that a P-ROM without any programmed cell should be offered to users. Accordingly, any defectiveness in the P-ROM does not appear until the programming is done by the user, who finds that the data program cannot be correctly performed. The malfunction of peripheral circuits or the defect in the memory cells themselves may make the data program impossible. However, even where the peripheral circuits and the memory cells have no defect, there occurs a phenomenon that the data program cannot be correctly carried out to the P-ROM of the junction destruction type. This phenomenon becomes remarkable as the memory capacity of the P-ROM increases. The inventors of the present invention have investigated the cause of the phenomenon, and discovered that the cause is a parasitic thyristor effect based on a particular geometrical relationship among the programmed and unprogrammed cells in the memory cell array. The parasitic thyristor effect occurs when the programmed and unprogrammed cells determined by the user take the particular geometrical relationship.